Electronic design automation (EDA) is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. EDA is also referred to as electronic computer-aided design (ECAD).
High-level synthesis (or behavioural synthesis, algorithmic synthesis) - high-level design description (e.g. in C/C++) is converted into RTL.
Logic synthesis - translation of RTL design description (e.g. written in Verilog or VHDL) into a discrete netlist of logic gates.
Schematic Capture For standard cell digital, analog, RF-like Capture CIS in Orcad by CADENCE and ISIS in Proteus
Layout, usually schematic-driven layout, like Layout in Orcad by Cadence, ARES in Proteus.
Transistor simulation – low-level transistor-simulation of a schematic/layout's behavior, accurate at device-level.
Logic simulation – digital-simulation of an RTL or gate-netlist's digital (boolean 0/1) behavior, accurate at boolean-level.
Behavioral Simulation – high-level simulation of a design's architectural operation, accurate at cycle-level or interface-level.
Hardware emulation – Use of special purpose hardware to emulate the logic of a proposed design. Can sometimes be plugged into a system in place of a yet-to-be-built chip; this is called in-circuit emulation.
Technology CAD simulate and analyze the underlying process technology. Electrical properties of devices are derived directly from device physics.
Electromagnetic field solvers, or just field solvers, solve Maxwell's equations directly for cases of interest in IC and PCB design. They are known for being slower but more accurate than the layout extraction above.
Schematic capture program
Clock Domain Crossing Verification (CDC check): Similar to linting, but these checks/tools specialize in detecting and reporting potential issues like data loss, meta-stability due to use of multiple clock domains in the design.
Formal verification, also model checking: Attempts to prove, by mathematical methods, that the system has certain desired properties, and that certain undesired effects (such as deadlock) cannot occur.
Mask data preparation, MDP: generation of actual lithography photomask used to physically manufacture the chip.
Resolution enhancement techniques, RET – methods of increasing of quality of final photomask.
Optical proximity correction, OPC – up-front compensation for diffraction and interference effects occurring later when chip is manufactured using this mask.
Mask generation – generation of flat mask image from hierarchical design.
Automatic test pattern generation, ATPG – generates pattern-data to systematically exercise as many logic-gates, and other components, as possible.
Built-in self-test, or BIST – installs self-contained test-controllers to automatically test a logic (or memory) structure in the design